3D 封装中硅通孔的电–热–结构耦合分析

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工程热物理学报 ›› 2024, Vol. 45 ›› Issue (11) : 3508-3516.

张远乐, 龚瑜璠, 陈召川, 赵起, 孟欣, 李强, 陈雪梅

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Electrical-thermal-structural Coupling Analysis of Through Silicon Vias in 3D Packaging

ZHANG Yuanle, GONG Yufan, CHEN Zhaochuan, ZHAO Qi, MENG Xin, LI Qiang, CHEN Xuemei

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摘要

本文利用有限元分析软件对3D 集成芯片中不同形状的硅通孔(TSV) 结构进行电–热–结构耦合分析。研究结果表明：圆环形TSV 的应力水平远小于圆柱形和圆锥形TSV。在相同激励电压下，减小TSV 直径、增大TSV 高度、减小SiO₂厚度均可提高TSV 的可靠性。对圆环形TSV 进行正交实验发现，TSV 的直径和中间介质对最高温度、最大应力影响程度较大。在单层TSV 阵列中，当中心间距较小时，圆环形TSV 出现应力叠加现象，应力叠加水平受中心间距与排列方式的影响。

Abstract

In this paper, the electric-thermal-structural coupling analysis of different structures of through silicon via (TSV) with different shapes in 3D integrated chips is performed with finite element analysis (FEA) software. The results reveal that the stress level of circular TSV is much smaller than cylindrical and conical TSV. At the same excitation voltage, the reliability of TSV can be improved by decreasing the TSV diameter, increasing the TSV height, and decreasing the thickness of SiO₂. The orthogonal experiments on circular TSV indicate that a greater effect of the diameter and intermediate medium of the TSV on the maximum temperature and maximum stress is achieved. In single-layer TSV arrays, the phenomenon of stress superposition is observed in circular TSV when the centre spacing was small, and the level of stress superposition is affected by the center spacing and array arrangement.

导出引用

张远乐, 龚瑜璠, 陈召川, 赵起, 孟欣, 李强, 陈雪梅. 3D 封装中硅通孔的电–热–结构耦合分析[J]. 工程热物理学报, 2024, 45(11): 3508-3516

ZHANG Yuanle, GONG Yufan, CHEN Zhaochuan, ZHAO Qi, MENG Xin, LI Qiang, CHEN Xuemei. Electrical-thermal-structural Coupling Analysis of Through Silicon Vias in 3D Packaging[J]. Journal of Engineering Thermophysics, 2024, 45(11): 3508-3516

中图分类号： TK02

基金

国家自然科学基金资助项目(No.U2241252，No.52276071)

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出版日期
2024-10-26
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2025-01-08

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